1. Field of Invention
The present invention relates to a control chip having a defer queue and a method of operating the control chip. More particularly, the present invention relates to control chip having a multiple-layer defer queue and a method of operating the control chip.
2. Description of Related Art
At present, personal computer has a central processing unit (CPU) that connects with a control chip through a high-speed CPU bus. The control chip is connected to an AGP bus and one or more PCI buses. The PCI buses may couple with a number of PCI compatible peripheral devices or memory units. Since the CPU is at the core of a personal computer, any requests from the CPU through the PCI bus must be processed quickly and do not affect other requests demanded by the CPU are unaffected. In fact, fast response to a request is one of the factors that indicates the operating efficiency of a computer system.
Requests sent from the CPU to a PCI bus through the control chip can be grouped together under two major types. The first type includes requests such as input/output read (IOR), input/output write (IOW) and memory read (MEMR) and the second type includes requests such as memory write (MEMW). For the requests belonging to the first type, the CPU must obtain a response from the PCI bus in order to complete the transaction with respect to the first type request. For example, the control chip needs to receive requested data from the PCI bus before transmitting the requested data to the CPU. However, for a request belonging to the second type, the control chip has a buffer for holding the request. There is no need for the request to be immediately sent out. The control chip may respond directly to the CPU, and the central processing unit then regards that the transaction with respect to the second type request has been complete.
A conventional control chip only has a built-in one-layered defer queue (DFQ). When the CPU issues a request belonging to the first type and the corresponding defer bit is enabled (i.e. CPU request meets defer condition), the control chip will transfer the request to the DFQ for storage. Also and, a defer response is issued to inform the CPU that this request satisfies the defer condition. After the requested response data is transferred back via the PCI bus, the control chip initiates the transmission of requested response data to the CPU according to the stored requested data in the DFQ. This arrangement obviates the need for continuous retry of the CPU or occupation of the CPU bus for too long just to complete a CPU instruction. Ultimately, operating efficiency of the computer system is increased.
However, the one-layered defer queue can only process one defer transaction that meets the defer conditions. When the CPU issues a first-type request and the DFQ has already been occupied, then the control chip will issue a retry response to the CPU, causing the CPU to continuously issue the request to the control chip until the DFQ has space. Hence, overall performance of the system decreases.
In brief, conventional method for processing request from the CPU has the following drawbacks:
1. DFQ only has an one-layer when the DFQ is occupied, the CPU needs to repeatedly issue the request until the DFQ has space, due to the effect of retry. This slows down the operating speed of the system.
2. When the CPU issues a request belonging to the first type while the defer bit is still not enabled, due to that the DFQ of the control chip cannot store the first type request, the control chip will repeatedly issue retry response to the CPU. As a result, the CPU repeatedly issues the request to the control chip. This manner reduces the performance and efficiency of the whole system.